VTS 2007 - Call for Participation

CALL FOR PARTICIPATION

LAST CHANCE TO TAKE ADVANTAGE OF DISCOUNTED VTS 2007 ROOM RATES
Room Rates At the Claremont Resort Will Increase After APRIL 13, 2007

ONLINE REGISTRATION IS NOW AVAILABLE AT: https://www.cemamerica.com/vts2007/
Advance Registration Rates End April 23, 2007

Program Highlights -- More Information -- Committees

Program Highlights

The IEEE VLSI Test Symposium explores emerging trends and novel concepts in the testing of integrated circuits and systems. The symposium is a leading international forum where many of the world's leading test experts and professionals from both industry and academia join to present and debate key issues in testing. VTS 2007 addresses key trends and challenges in the semiconductor design and manufacturing industries through an exciting program that includes Keynote and Plenary Talks, Technical Paper Sessions, Embedded Tutorials, Panels, Hot Topic Sessions, Full-day Tutorials, co-located Workshops, and the Innovative Practices Track.

TECHNICAL PAPER SESSIONS will present the latest research results in test. VTS 2007 technical paper sessions include:

RF Test
Delay Test Quality
Memory Test
Test Compression
Going After Defects
Online Test
Diagnosis
ATPG for Delay Faults
Advances in Test
Failure Estimation
Fault Prediction & Evaluation
Yield Diagnostics Solutions
Analog Test
High Level Test Techniques
Memory Repair
SOC Test
RF Test II
Design for Test
Testing Large Chips
Ensuring Secure Chips

INNOVATIVE PRACTICES (IP) TRACK highlights cutting-edge challenges faced by test practitioners, and innovative solutions employed to address them, including:

Design in Presence of Variations: Characterization, Monitoring, and Response
Small Delay Test in Practice
System Test and NTFs
High-Speed Test
Testing Alone Isn't Enough: Reliability Challenges in Scaled CMOS
Impact of New Memory Failure Modes
Collaborative DFT Practices Needed for Low-cost Testing
Board and System Level Memory Test Problems and Proposed Solutions

SPECIAL SESSIONS will include:

EMBEDDED TUTORIALS: Statistical and Data Mining Methods for Test-Based Yield Learning
HOT TOPIC SESSIONS: Fault Tolerant Nanoscale Architectures - the Challenges and Emerging Solutions; Making Analog & Mixed Signal Testing As Robust As Digital; Testing in the Presence of NOCs
NEW TOPIC: From Asynchronous Electronics to Asynchronous Molecular Nanoelectronics
PANELS: Conversations With Test Experts; RF Yield: Is It A Problem?
AWARD SESSION: TTTC 2007 Best Doctoral Thesis Award

FULL-DAY TUTORIALS and WORKSHOPS complement the core technical program of VTS.

WORKSHOPS:
Open Source Test Technology Tools Workshop
Wireless Test Workshop

TUTORIALS:
Scan Delay Testing of Nanometer SOCs
Dealing with Timing Issues for sub-100n Designs - from Modeling to Mass Production
DFX: The Convergence of Yield, Manufacturing, and Test

The social program at VTS provides an opportunity for informal technical discussions among participants. Berkeley, California, provides a very attractive backdrop for all VTS 2007 activities. We are sure that you will find VTS 2007 enlightening, thought-provoking, rewarding, and enjoyable!

More Information

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For more information contact:

GENERAL CHAIR
Paolo Prinetto
Politecnico di Torino
Dip. di Automatica e Informatica
Corso Duca degli Abruzzi 24
I-10129 Torino TO, Italy.
T: +39-011-564-7007
E: Paolo.Prinetto@polito.it

PROGRAM CHAIR
Alex Orailoglu
University of California, San Diego
Dept. of Computer Science and Eng.
9500 Gilman Drive, Mail Code 0114
La Jolla, CA 92093-0114, USA
T: +1-858-534-0914
E: alex@cs.ucsd.edu

Committees

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General Chair
P. Prinetto - Poli. di Torino

Program Chair
A. Orailoglu - UC San Diego

Vice-General Co-Chairs
S. M. Reddy - U Iowa
H.-J. Wunderlich - U Stuttgart

Vice-Program Co-Chairs
J. Segura - U Illes Balears
B. West - Credence

New Topics
B. Courtois - TIMA

Special Sessions
P. Maxwell - Avago
C. Metra - U Bologna

Innovative Practices Track
K. Hatayama - Renesas
S. Mitra - Intel

Publicity
A. Raghunathan - NEC

Audio/Visual
D. Gizopoulos - U Piraeus

Finance
M. Abadir - Freescale

Publications
S. Ravi - NEC

Local Arrangements
M. Renovell - LIRMM

Ex-Officio
Y. Zorian - Virage Logic

Steering Committee
J. Figueras - U Poli. Catalunya
A. Ivanov - UBC
M. Nicolaidis - TIMA
R. Roy - Zenasis
A. Singh - Auburn U
P. Varma - Blue Pearl
Y. Zorian - Virage Logic

Program Committee
J. A. Abraham - UT Austin
V. D. Agrawal - Auburn U
L. Anghel - TIMA
D. Appello - STMicroelectronics
B. Becker - U Freiburg
A. Benso - Poli di Torino
L. Carro - UF Rio Grande do Sul
C.-H. Chiang - Lucent
D. Conti - IBM
B. Cory - nVidia
R. Galivanche - Intel
S. Gupta - USC
I. Harris - UC Irvine
S. Hellebrand - U Paderborn
B. Kaminska - Pultronics
R. Kapur - Synopsys
A. Khoche - Verigy
H. Konuk - Broadcom
C. Landrault - LIRMM
X. Li - Chinese Academy of Sciences
R. Makki - UAE U
E.J. McCluskey - Stanford U
L. Milor - Georgia Tech
S. Mourad - Santa Clara U
P. Muhmenthaler - Infineon
Z. Navabi - Northeastern
J. Plusquellic - U Maryland
J. Rajski - Mentor Graphics
CP Ravikumar - TI
R. Segers - Philips
M. Soma - U Washington
S. Sunter - LogicVision
C. Thibeault - E Tech Sup Montreal
J. Tyszer - Poznan U Technology
R. Ubar - U Tallinn
C. -W. Wu - Nat Tsing Hua U
A. Yessayan - Virage Logic

For more information, visit us on the web at: http://www.tttc-vts.org

The 25th IEEE VLSI TEST SYMPOSIUM (VTS 2007) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	25th IEEE VLSI TEST SYMPOSIUM (VTS 2007) May 6th - May 10th, 2007 Claremont Resort, Berkeley, California, USA http://www.tttc-vts.org